Building this project requires a few prerequisite tools that stem from the GNU/Linux world, such as:
So if you are predominantly a windows developer and want to contribute to the project, but feel a bit overwhelmed at the thought of jumping ship to Linux, then installing Cygwin in your Windows environment can be a good compromise.
This walkthrough will try guide you through how it's done.
You can now run cygwin from “Start Menu » Programs » Cygwin » Cygwin Terminal”:
Run the Cygwin setup exe again and install the following packages:
For example, for “libpng-devel”, search for it via this step in the wizard and click on it so the “[x]” checkmark appears next to it.
Note that you can search and select multiple items this way prior to clicking on the wizard's “Next” button. (ie, you don't need to run the cygwin setup exe once per package, do all packages at once :))
The source code for the MEGA65 project is housed in a git repository hosted by github.
To retrieve it, inside the Cygwin Terminal, do the following:
The source-code will then be placed in the “~/mega65-core” path.
This refers to Michael Martin's Ophis Assembler.
It is a cross-compiler for the 6502-family of processors. Paul has tweaked it so that it can also support his new 4502 processor.
You'll need to grab it from Paul's github fork of Ophis, as follows:
NOTE: Ophis needs to be housed within the same parent-folder that you previously cloned the mega65 code to, as the mega65 code uses relative-paths to access it. So if you chose a different parent-folder for your mega65 code to that shown in these docs, make sure you put Ophis in that location too!
NOTE2: You won't need to compile Ophis as it is written in python. I believe the default Cygwin install comes with python. If you find this isn't the case for you, please install it via the cygwin setup exe.
GHDL is a vhdl simulator, allowing you to assess how the vhdl code behaves without having to wait an hour or so for the bitstream to build/synthesise.
It also needs to be built from the source, so here are some steps for getting it done.
You should start seeing cpu instructions being outputted to the screen as they are executed, something like the following:
gs4510.vhdl:915:9:@980ns:(report note): $8100 4C D3 8C jmp $8CD3 A:11 X:22 Y:33 Z:00 SP:BEFF P:24 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.. gs4510.vhdl:915:9:@1060ns:(report note): $8CD3 78 sei A:11 X:22 Y:33 Z:00 SP:BEFF P:24 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.. gs4510.vhdl:915:9:@1220ns:(report note): $8CD4 A9 00 lda #$00 A:00 X:22 Y:33 Z:00 SP:BEFF P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@1500ns:(report note): $8CD6 8D 00 BF sta $BF00 A:00 X:22 Y:33 Z:00 SP:BEFF P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@1900ns:(report note): $8CD9 4C E5 8C jmp $8CE5 A:00 X:22 Y:33 Z:00 SP:BEFF P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@2220ns:(report note): $8CE5 20 8E 8C jsr $8C8E A:00 X:22 Y:33 Z:00 SP:BEFD P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@2300ns:(report note): $8C8E 78 sei A:00 X:22 Y:33 Z:00 SP:BEFD P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@2380ns:(report note): $8C8F D8 cld A:00 X:22 Y:33 Z:00 SP:BEFD P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@2460ns:(report note): $8C90 03 see A:00 X:22 Y:33 Z:00 SP:BEFD P:26 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZ. gs4510.vhdl:915:9:@2540ns:(report note): $8C91 38 sec A:00 X:22 Y:33 Z:00 SP:BEFD P:27 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZC gs4510.vhdl:915:9:@2860ns:(report note): $8C92 20 EC 95 jsr $95EC A:00 X:22 Y:33 Z:00 SP:BEFB P:27 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZC gs4510.vhdl:915:9:@3180ns:(report note): $95EC B0 06 bcs $95F4 A:00 X:22 Y:33 Z:00 SP:BEFB P:27 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.IZC gs4510.vhdl:915:9:@3340ns:(report note): $95F4 A9 47 lda #$47 A:47 X:22 Y:33 Z:00 SP:BEFB P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@3620ns:(report note): $95F6 8D 2F D0 sta $D02F A:47 X:22 Y:33 Z:00 SP:BEFB P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@3780ns:(report note): $95F9 A9 53 lda #$53 A:53 X:22 Y:33 Z:00 SP:BEFB P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@4060ns:(report note): $95FB 8D 2F D0 sta $D02F A:53 X:22 Y:33 Z:00 SP:BEFB P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@4460ns:(report note): $95FE 60 rts A:53 X:22 Y:33 Z:00 SP:BEFD P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@4860ns:(report note): $8C95 AD 31 D0 lda $D031 A:61 X:22 Y:33 Z:00 SP:BEFD P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C gs4510.vhdl:915:9:@5020ns:(report note): $8C98 09 40 ora #$40 A:61 X:22 Y:33 Z:00 SP:BEFD P:25 $01=F5 MAPLO:4000 MAPHI:3F00 ..E-.I.C